The present disclosure relates generally to computer processor design, and more specifically to a method and system for synchronizing signals traveling between a plurality of clock domains.
In an electronic system, it is common to have various sections of synchronous logic circuits operating with different clocks, which are usually not synchronized with each other. Each area of a circuit operated according to a local clock, unsynchronized with other local clocks. Often it is necessary to pass data between different clock domains. A common method for synchronizing data is to use a double-buffer circuit, which uses two flip-flops. A first flip-flop clocks an input signal in sync with a first clock in a first clock domain (or a first time domain), and a second flip-flop clocks the output of the first flip-flop in sync with a second clock in a second clock domain.
Not all clock domains are constantly active. For example, if the first clock domain is not active, then the second flip-flop will not need to be active. For instance, if the first clock domain has a controller centric circuit which is used to support external debugging, the signal coming out from the first clock domain does not need to be active all the time. However, under normal conditions, the second flip-flop continues to be active and will unnecessarily consume energy. This is extremely wasteful in view of the fact that there are usually a large number of flip-flops in the second clock domain that will participate the circuit operation.
Accordingly, there is a need for an improved synchronizing system that is able to detect whether the clock from a clock domain is active, and is able to activate and deactivate certain related circuits depending on the activity of the clock.